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Reverse Engineering Digital Circuits Using Structural and Functional Analyses.

, , , , , , , , and . IEEE Trans. Emerg. Top. Comput., 2 (1): 63-80 (2014)

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Challenges in code generation for embedded processors., , , , , , , and . Code Generation for Embedded Processors, page 48-64. Kluwer, (1994)Code generation for fixed-point DSPs., and . ACM Trans. Design Autom. Electr. Syst., 3 (2): 136-161 (1998)Performance estimation of embedded software with instruction cache modeling., , and . ACM Trans. Design Autom. Electr. Syst., 4 (3): 257-279 (1999)A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs., and . ACM Trans. Design Autom. Electr. Syst., 12 (1): 6:1-6:24 (2007)Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification., , , , , and . CoRR, (2018)Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1692-1705 (2018)Security Verification of Low-Trust Architectures., , , , , , and . CCS, page 945-959. ACM, (2023)Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models., , and . ASP-DAC, page 154-159. IEEE, (2022)Power-driven Design of Router Microarchitectures in On-chip Networks., , and . MICRO, page 105-116. IEEE Computer Society, (2003)Processor Evaluation in an Embedded Systems Design Environment., , , and . VLSI Design, page 98-103. IEEE Computer Society, (2000)