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High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 4886-4897 (2022)A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs., , and . IEEE Access, (2022)A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates., , , , and . PRIME, page 21-24. IEEE, (2023)High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain., , , and . PRIME, page 69-72. IEEE, (2022)A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages., , , , and . Int. J. Circuit Theory Appl., 51 (5): 1971-1987 (May 2023)SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks., , and . Cryptogr., 5 (3): 16 (2021)A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations., , , , and . IEEE Access, (2023)A Novel Ultra-Compact FPGA PUF: The DD-PUF., , and . Cryptogr., 5 (3): 23 (2021)A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability., and . Cryptogr., 7 (2): 18 (June 2023)Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design., , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (12): 4689-4693 (2022)