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Formalizing Timing Diagram Requirements in Discrete Duration Calculus.

, , and . SEFM, volume 10469 of Lecture Notes in Computer Science, page 253-268. Springer, (2017)

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Averaging in LTL., , and . CONCUR, volume 8704 of Lecture Notes in Computer Science, page 266-280. Springer, (2014)DCSynth: Guided Reactive Synthesis with Soft Requirements., , and . VSTTE, volume 12031 of Lecture Notes in Computer Science, page 124-142. Springer, (2019)Conflict-tolerant specifications in temporal logic., , and . ISEC, page 103-110. ACM, (2010)Formalizing Timing Diagram Requirements in Discrete Duration Calulus., , and . CoRR, (2017)Formalizing Timing Diagram Requirements in Discrete Duration Calculus., , and . SEFM, volume 10469 of Lecture Notes in Computer Science, page 253-268. Springer, (2017)DCSYNTH: A Tool for Guided Reactive Synthesis with Soft Requirements., , and . CoRR, (2019)A Compositional Hierarchical Monitoring Automaton Construction for LTL., and . ICTAC, volume 7521 of Lecture Notes in Computer Science, page 16-29. Springer, (2012)