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Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry., , , , , , , , and . ESSCIRC, page 63-66. IEEE, (2021)Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures., , , , , , , , and . IRPS, page 1-6. IEEE, (2020)Scaled contact length with low contact resistance in monolayer 2D channel transistors., , , , , , , , , and 16 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Circuit models for the co-simulation of superconducting quantum computing systems., , , , , , , and . DATE, page 968-973. IEEE, (2021)Building high performance transistors on carbon nanotube channel., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS., , , , , , , , , and . VLSI Technology and Circuits, page 403-404. IEEE, (2022)WS2 transistors on 300 mm wafers with BEOL compatibility., , , , , , , , , and 8 other author(s). ESSDERC, page 212-215. IEEE, (2017)Material selection and device design guidelines for two-dimensional materials based TFETs., , , , , , and . ESSDERC, page 54-57. IEEE, (2017)Tunnel FETs using Phosphorene/ReS2 heterostructures., , , , , and . DRC, page 113-114. IEEE, (2019)System-level assessment and area evaluation of Spin Wave logic circuits., , , , , , , and . NANOARCH, page 25-30. IEEE Computer Society/ACM, (2014)