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Disambiguation of "Okada, Kenichi"

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F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power.

, , , and . IEICE Trans. Electron., 105-C (3): 118-125 (2022)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kenichi Ishikawa

Kenichi Kida

Kenichi Moriya

Naotake Okada

Hinoto Okada

 

Other publications of authors with the same name

Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing., , and . IEEE J. Solid State Circuits, 48 (2): 429-440 (2013)A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount., , , , , , , , , and 4 other author(s). IEEE Access, (2023)Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 48 (1): 46-65 (2013)A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios., , , , and . IEEE J. Solid State Circuits, 49 (9): 1984-1994 (2014)A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer., , , , , and . IEEE J. Solid State Circuits, 57 (4): 1211-1223 (2022)A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 55 (9): 2371-2386 (2020)A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications., , , , , and . IEEE J. Solid State Circuits, 43 (4): 1020-1029 (2008)Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference., , , , and . IEEE J. Solid State Circuits, 50 (12): 2799-2803 (2015)A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 603-616 (2021)Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector., , , , and . IEICE Trans. Electron., 102-C (7): 520-529 (2019)