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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

M. Rasch, C. Mackin, M. Gallo, A. Chen, A. Fasoli, F. Odermatt, N. Li, S. Nandakumar, P. Narayanan, H. Tsai, G. Burr, A. Sebastian, and V. Narayanan. CoRR, (2023)

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S. R. Keshava

Ramya Nandakumar

Kannabiran Nandakumar

Murti von R S Devarakonda

Teresa S L R A Terreri

Other publications of authors with the same name

Bio-mimetic Synaptic Plasticity and Learning in a sub-500mV Cu/SiO2/W Memristor.S. Nandakumar, and B. Rajendran. CoRR, (2020)Mixed-precision training of deep neural networks using computational memory.S. Nandakumar, M. Gallo, I. Boybat, B. Rajendran, A. Sebastian, and E. Eleftheriou. CoRR, (2017)Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses.S. Nandakumar, I. Boybat, M. Gallo, E. Eleftheriou, A. Sebastian, and B. Rajendran. CoRR, (2019)Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.M. Rasch, C. Mackin, M. Gallo, A. Chen, A. Fasoli, F. Odermatt, N. Li, S. Nandakumar, P. Narayanan, H. Tsai and 3 other author(s). CoRR, (2023)Computational memory-based inference and training of deep neural networks.A. Sebastian, I. Boybat, M. Dazzi, I. Giannopoulos, V. Jonnalagadda, V. Joshi, G. Karunaratne, B. Kersting, R. Khaddam-Aljameh, S. Nandakumar and 6 other author(s). VLSI Circuits, page 168-. IEEE, (2019)Neuromorphic computing with multi-memristive synapses.I. Boybat, M. Gallo, S. Nandakumar, T. Moraitis, T. Parnell, T. Tuma, B. Rajendran, Y. Leblebici, A. Sebastian, and E. Eleftheriou. CoRR, (2017)HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs.R. Khaddam-Aljameh, M. Stanisavljevic, J. Mas, G. Karunaratne, M. Brändli, F. Liu, A. Singh, S. Müller, U. Egger, A. Petropoulos and 14 other author(s). IEEE J. Solid State Circuits, 57 (4): 1027-1038 (2022)Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation.R. Bruce, S. Sarwat, I. Boybat, C. Cheng, W. Kim, S. Nandakumar, C. Mackin, T. Philip, Z. Liu, K. Brew and 21 other author(s). IRPS, page 1-6. IEEE, (2021)Live demonstration: Spiking neural circuit based navigation inspired by C. elegans thermotaxis.C. Shetty, S. Nitchith, R. Rawat, S. Nandakumar, P. Shah, S. Kulkarni, and B. Rajendran. ISCAS, page 1905. IEEE, (2015)An efficient synaptic architecture for artificial neural networks.I. Boybat, M. Gallo, S. Nandakumar, T. Moraitis, T. Tuma, B. Rajendran, Y. Leblebici, A. Sebastian, and E. Eleftheriou. NVMTS, page 1-4. IEEE, (2017)

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Disambiguation of "Nandakumar, S. R."

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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

Please choose a person to relate this publication to

S. R. Keshava

Ramya Nandakumar

Kannabiran Nandakumar

Murti von R S Devarakonda

Teresa S L R A Terreri

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nandakumar, S. R."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

Please choose a person to relate this publication to

S. R. Keshava

Ramya Nandakumar

Kannabiran Nandakumar

Murti von R S Devarakonda

Teresa S L R A Terreri

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.