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Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning Model., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (2): 564-568 (2022)A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes., , , , , and . IEICE Electron. Express, 14 (15): 20170660 (2017)OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit., , , , , and . ASICON, page 1-4. IEEE, (2023)A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (1): 106-110 (2019)ASIC Design Principle Course with Combination of Online-MOOC and Offline-Inexpensive FPGA Board., , , and . ACM Great Lakes Symposium on VLSI, page 431-436. ACM, (2021)A unioned graph neural network based hardware Trojan node detection., , , , , , , , , and . IEICE Electron. Express, 20 (13): 20230204 (2023)LC-KO: A congestion-aware and area&timing-oriented placement method., , , , and . ASICON, page 1-4. IEEE, (2015)NBLG: A Robust Legalizer for Mixed-Cell-Height Modern Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4681-4693 (2022)A Power and Area Efficient Lepton Hardware Encoder with Hash-based Memory Optimization., , , , , , and . CoRR, (2021)High Parallel VLSI Architecture Design of BPC in JPEG2000., , and . ASICON, page 1-4. IEEE, (2019)