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Optimizing power and performance for reliable on-chip networks., , , , , and . ASP-DAC, page 431-436. IEEE, (2010)Numerical limitations on the design of digit online networks., and . IEEE Symposium on Computer Arithmetic, page 156-161. IEEE Computer Society, (1983)Regular, area-time efficient carry-lookahead adders., and . IEEE Symposium on Computer Arithmetic, page 9-15. IEEE, (1985)Optimising power efficiency in trace cache fetch unit., , , and . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)Reducing non-deterministic loads in low-power caches via early cache set resolution., , and . Microprocess. Microsystems, 31 (5): 293-301 (2007)An edge-based heuristic for Steiner routing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (12): 1563-1568 (1994)Compiler-guided leakage optimization for banked scratch-pad memories., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1136-1146 (2005)Design and implementation of real time video processor., , , and . ICASSP, page 2215-2218. IEEE, (1986)Intermediate-level vision tasks on a memory array architecture., and . Mach. Vis. Appl., 6 (1): 50-65 (1992)Distributed Fault Diagnosis in the Butterfly Parallel Processor., , , and . ICPP (1), page 172-175. Pennsylvania State University Press, (1989)