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An efficient graph representation for arithmetic circuitverification., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (12): 1443-1454 (2001)On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication.. IEEE Trans. Computers, 40 (2): 205-213 (1991)TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories., and . Int. J. Embed. Syst., 1 (1/2): 134-149 (2005)Bit-Level Analysis of an SRT Divider Circuit.. DAC, page 661-665. ACM Press, (1996)Automatic Clock Abstraction from Sequential Circuits., , and . DAC, page 707-711. ACM Press, (1995)A Performance Study of BDD-Based Model Checking., , , , , , , and . FMCAD, volume 1522 of Lecture Notes in Computer Science, page 255-289. Springer, (1998)Revisiting Positive Equality., , , and . TACAS, volume 2988 of Lecture Notes in Computer Science, page 1-15. Springer, (2004)Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods., and . CAV, volume 2725 of Lecture Notes in Computer Science, page 154-166. Springer, (2003)Modeling and Verification of Out-of-Order Microprocessors in UCLID., , and . FMCAD, volume 2517 of Lecture Notes in Computer Science, page 142-159. Springer, (2002)Silicon Compilers: How Well Have They Done, and Where Are They Headed?. IFIP Congress, page 379. North-Holland/IFIP, (1989)