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SCANN: Synthesis of Compact and Accurate Neural Networks.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 3012-3025 (2022)

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Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption., and . ESA/VLSI, page 63-69. CSREA Press, (2004)Detecting Multiple Faults in CMOS Circuits.. ITC, page 514-519. IEEE Computer Society, (1986)Synthesis of Fault Tolerant Architectures for Molecular Dynamics., and . ISCAS, page 247-250. IEEE, (1994)Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems., and . ISCAS, page 333-336. IEEE, (1994)Smart Healthcare., , , and . Foundations and Trends in Electronic Design Automation, 12 (4): 401-466 (2018)NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm., , and . CoRR, (2017)Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 136-143 (1991)Generation of distributed logic-memory architectures through high-level synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1694-1711 (2005)Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2193-2206 (2006)Fast Design Space Exploration of Nonlinear Systems: Part II., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 2984-2999 (2022)