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CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors.

, , , , and . Microelectron. Reliab., 54 (5): 1009-1021 (2014)

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MultiObjective GPU design space exploration optimization., , and . HPCS, page 659-666. IEEE, (2016)Optimum Power-Performance GPU Configuration Prediction Based on Code Attributes., , and . HPCS, page 418-425. IEEE, (2017)Branchless cycle prediction for embedded processors., and . SAC, page 928-932. ACM, (2006)Rethinking Prefetching in GPGPUs: Exploiting Unique Opportunities., and . HPCC/CSS/ICESS, page 72-77. IEEE, (2015)TELEPORT: Hardware/software alternative to CUDA shared memory programming., , and . Microprocess. Microsystems, (2018)Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols., , and . Conf. Computing Frontiers, page 259-266. ACM, (2007)A Power-Aware Alternative for the Perceptron Branch Predictor., and . Asia-Pacific Computer Systems Architecture Conference, volume 4697 of Lecture Notes in Computer Science, page 198-208. Springer, (2007)Energy Efficient On-Demand Dynamic Branch Prediction Models., , , , , and . IEEE Trans. Computers, 69 (3): 453-465 (2020)Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors., , and . ISCA Workshops, volume 6161 of Lecture Notes in Computer Science, page 211-221. Springer, (2010)EFL-Net: An Efficient Lightweight Neural Network Architecture for Retinal Vessel Segmentation., and . VISIGRAPP (4: VISAPP), page 920-927. SCITEPRESS, (2023)