Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Sizing Digital Circuits Using Convex Optimization Techniques., and . Computational Intelligence in Digital and Network Designs and Applications, Springer, (2015)ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules., , , , , and . ISPD, page 147-151. ACM, (2019)Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes., , , and . ISPD, page 154-161. ACM, (2013)Optimal gate sizing using a self-tuning multi-objective framework., , , and . Integr., 47 (3): 347-355 (2014)Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (4): 532-545 (2014)A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications., , , and . ACM Great Lakes Symposium on VLSI, page 305-310. ACM, (2013)A New Length-Based Algebraic Multigrid Clustering Algorithm., , , and . VLSI Design, (2012)A pre-placement individual net length estimation model and an application for modern circuits., , , and . Integr., 44 (2): 111-122 (2011)Analysis of post-placement length estimation., , , and . SLIP, page 23. ACM, (2012)A new a priori net length estimation technique for integrated circuits using radial basis functions., , , , and . Comput. Electr. Eng., 39 (4): 1204-1218 (2013)