( en | de | ru )

 

Disambiguation of "Chakradhar, Srimat T."

Author of the publication

copydeleteadd this publication to your clipboard
Scalable Effort Hardware Design.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (9): 2004-2016 (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chakradhar Narayan Sinha

T Peters

T Frieberg

T Neumann

T Weber

 

Other publications of authors with the same name

Supporting GPU sharing in cloud environments with a transparent runtime consolidation framework., , , and . HPDC, page 217-228. ACM, (2011)A virtual memory based runtime to support multi-tenancy in clusters with GPUs., , , , , and . HPDC, page 97-108. ACM, (2012)Test Set Compaction Using Relaxed Subsequence Removal., and . J. Electron. Test., 16 (4): 319-327 (2000)A Methodology for Architectural Design of Multimedia Multiprocessor SoCs., , , , , and . IEEE Des. Test Comput., 22 (1): 18-26 (2005)Combinational ATPG theorems for identifying untestable faults in sequential circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (9): 1155-1160 (1995)Energy models for delay testing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (6): 728-739 (1995)Test function embedding algorithms with application to interconnected finite state machines., , and . EURO-DAC, page 219-224. IEEE Computer Society, (1993)Semi-automatic restructuring of offloadable tasks for many-core accelerators., , , and . SC, page 12:1-12:12. ACM, (2013)Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2193-2206 (2006)A solvable class of quadratic 0-1 programming., and . Discret. Appl. Math., 36 (3): 233-251 (1992)