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A hierarchical 3-D floorplanning algorithm for many-core CMP networks.

, and . ISCAS, page 1211-1214. IEEE, (2011)

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A hierarchical 3-D floorplanning algorithm for many-core CMP networks., and . ISCAS, page 1211-1214. IEEE, (2011)Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (1): 2-15 (2015)3D NOC for many-core processors., , , and . Microelectron. J., 42 (12): 1380-1390 (2011)Sneak path testing and fault modeling for multilevel memristor-based memories., , and . ICCD, page 215-220. IEEE Computer Society, (2013)Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 822-834 (2015)Analysis of Power-Oriented Fault Injection Attacks on Spiking Neural Networks., , , , , and . DATE, page 861-866. IEEE, (2022)Sneak-path Testing of Memristor-based Memories., , , and . VLSI Design, page 386-391. IEEE Computer Society, (2013)SCANN: Side Channel Analysis of Spiking Neural Networks., , , , and . Cryptogr., 7 (2): 17 (June 2023)Secure Memristor-based Main Memory., , and . DAC, page 178:1-178:6. ACM, (2014)Engineering crossbar based emerging memory technologies., , , and . ICCD, page 478-479. IEEE Computer Society, (2012)