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Disambiguation of "Ferrandi, Fabrizio"

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High-Level Synthesis Developments in the Context of European Space Technology Research (Invited Talk).

, , , , and . PARMA-DITAM, volume 116 of OASIcs, page 1:1-1:12. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2024)

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Fabrizio Catanese

Fabrizio Gabbiani

Fabrizio Gabrielli

Fabrizio Lindner

Fabrizio Arosio

 

Other publications of authors with the same name

Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks., , , , , and . DFT, page 223-230. IEEE Computer Society, (1993)An Expert Solution to Functional Testability Analysis of VLSI Circuits., , , , , and . SEKE, page 263-265. Knowledge Systems Institute, (1993)SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels., , , , , , , , , and 3 other author(s). ARCS Workshops, VDE-Verlag, (2011)Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis., , and . IEEE Des. Test, 35 (5): 54-62 (2018)Symbolic optimization of interacting controllers based onredundancy identification and removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 760-772 (2000)A design methodology to implement memory accesses in high-level synthesis., , and . CODES+ISSS, page 49-58. ACM, (2011)An Interrupt Controller for FPGA-based Multiprocessors., , , , , , and . ICSAMOS, page 82-87. IEEE, (2007)Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA., , , , , , and . ICSAMOS, page 107-114. IEEE, (2006)End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators., , , , , , , , , and 1 other author(s). IEEE Trans. Computers, 71 (12): 3074-3087 (2022)