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Disambiguation of "Zashcholkin, Kostiantyn"

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Formation of the Interval Stego Key for the Digital Watermark Used in Integrity Monitoring of FPGA-based Systems.

, , , and . IntelITSIS, volume 2623 of CEUR Workshop Proceedings, page 267-276. CEUR-WS.org, (2020)

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An Increase in Trustworthiness of Result Checking in Arithmetic Components of Embedded Systems., , , and . ICTES, volume 2516 of CEUR Workshop Proceedings, page 177-189. CEUR-WS.org, (2019)Combined Use of Equivalent and Non-Equivalent Transformations of FPGA Program Code to Embedding Additional Security Data., , , and . EWDTS, page 1-5. IEEE, (2021)Development of ICT Models in Area of Safety Education., , , , and . EWDTS, page 1-6. IEEE, (2020)Resilient Development of Models and Methods in Computing Space., , , , and . EWDTS, page 1-6. IEEE, (2021)Co-Embedding Additional Security Data and Obfuscating Low-Level FPGA Program Code., , , , and . EWDTS, page 1-5. IEEE, (2020)A Method to Improve FPGA Project Checkability for Safety-Related Applications., , , , , and . ICST, volume 2711 of CEUR Workshop Proceedings, page 150-160. CEUR-WS.org, (2020)Particularities of Sync Monitoring in FPGA Components of Safety-Related Systems., , , , and . IDAACS, page 979-983. IEEE, (2021)The Basic Model of Attack Resistance Estimation for Monitoring the Program Code Integrity of the FPGA-Based Systems., , , , and . IDAACS, page 234-238. IEEE, (2019)Development of Checkability in FPGA Components of Safety-Related Systems., , , , and . ICTES, volume 2762 of CEUR Workshop Proceedings, page 30-42. CEUR-WS.org, (2020)Augmented Checkability of LUT-oriented Circuits in FPGA-based Components of Safety-Related Systems., , , , and . IntelITSIS, volume 3156 of CEUR Workshop Proceedings, page 474-483. CEUR-WS.org, (2022)