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Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction.

, and . Computer, 32 (11): 42-45 (1999)

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Functional Approaches to Generating Orderings for Efficient Symbolic Representations., , and . DAC, page 624-627. IEEE Computer Society Press, (1992)Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes., and . IEEE Trans. Computers, 41 (12): 1580-1588 (1992)Fast functional evaluation of candidate OBDD variable orderings., , , and . EURO-DAC, page 4-10. EEE Computer Society, (1991)An ATE assisted DFD technique for volume diagnosis of scan chains., , , and . DAC, page 31:1-31:6. ACM, (2013)Speed Binning with Path Delay Test in 150-nm Technology., , and . IEEE Des. Test Comput., 20 (5): 41-45 (2003)Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (7): 1185-1195 (2015)DFT MAX and Power., , , , , , , , , and 2 other author(s). J. Low Power Electron., 3 (2): 199-205 (2007)Evaluation of Entropy Driven Compression Bounds on Industrial Designs., , , , and . ATS, page 13-18. IEEE Computer Society, (2008)Not All Xs are Bad for Scan Compression., and . ATS, page 7-12. IEEE Computer Society, (2008)Manufacturing Test of SoCs., and . Asian Test Symposium, page 317-319. IEEE Computer Society, (2002)