Author of the publication

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (5): 896-906 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Case Study: Efficient SDD test generation for very large integrated circuits., , , , and . VTS, page 78-83. IEEE Computer Society, (2011)Critical Paths Selection and Test Cost Reduction Considering Process Variations., and . Asian Test Symposium, page 259-264. IEEE Computer Society, (2013)Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes., , , , , , , , , and . DDECS, page 376-381. IEEE Computer Society, (2010)Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation., , , and . DATE, page 1172-1177. ACM, (2008)Secure Split-Test for preventing IC piracy by untrusted foundry and assembly., , and . DFTS, page 196-203. IEEE Computer Society, (2013)Case study: Detecting hardware Trojans in third-party digital IP cores., and . HOST, page 67-70. IEEE Computer Society, (2011)Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.. DFT, page 305-313. IEEE Computer Society, (2005)Securing Scan Design Using Lock and Key Technique., , , and . DFT, page 51-62. IEEE Computer Society, (2005)SCT: An Approach For Testing and Configuring Nanoscale Devices., and . VTS, page 370-377. IEEE Computer Society, (2006)Enhanced launch-off-capture transition fault testing., , and . ITC, page 10. IEEE Computer Society, (2005)