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A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs.

, , and . DATE, page 172-177. IEEE, (2009)

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Ultra-low swing CMOS transceiver for 2.5-D integrated systems., and . ISQED, page 262-267. IEEE, (2018)Mismatch Compensation Technique for Inverter-Based CMOS Circuits., and . ISCAS, page 1-5. IEEE, (2018)Voltage scaling for 3-D ICs: When, how, and how much?, and . Microelectron. J., (2017)An Enhanced Design Methodology for Resonant Clock Trees., , , and . J. Low Power Electron., 9 (2): 198-206 (2013)Fabrication Cost Analysis for Contactless 3-D ICs., , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (5): 758-762 (2019)Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (3): 837-843 (2021)TSV-based hairpin bandpass filter for 6G mobile communication applications., , , , , and . IEICE Electron. Express, 18 (15): 20210247 (2021)Application performance improvement by exploiting process variability on FPGA devices., , , , and . DATE, page 452-457. IEEE, (2017)PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs., , , and . FPGA, page 190. ACM, (2019)Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators., , , , and . ASP-DAC, page 709-714. ACM, (2021)