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Disambiguation of "Sherlekar, Sunil D."

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A Methodology for Designing Optimal Self-Checking Sequential Circuits.

, , and . ITC, page 283-291. IEEE Computer Society, (1991)

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C Sunil Kumar

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Other publications of authors with the same name

A Methodology for Designing Optimal Self-Checking Sequential Circuits., , and . ITC, page 283-291. IEEE Computer Society, (1991)Parallel Computing Goes Mainstream.. IC3, volume 306 of Communications in Computer and Information Science, page 4-5. Springer, (2012)Power Reduction Techniques for Portable DSP Applications., and . VLSI Design, page 3. IEEE Computer Society, (2000)Low power realization of FIR filters using multirate architectures., , and . VLSI Design, page 370-375. IEEE Computer Society, (1996)State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits., , and . VLSI Design, page 15-20. IEEE Computer Society, (1993)Synthesis of multiplier-less FIR filters with minimum number of additions., , and . ICCAD, page 668-671. IEEE Computer Society / ACM, (1995)A new methodology for the design of low-cost fail safe circuits and networks., , , , and . VLSI Design, page 355-358. IEEE Computer Society, (1995)Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters., , and . VLSI Design, page 124-129. IEEE Computer Society, (1997)Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters., , , and . VLSI Design, page 110-115. IEEE Computer Society, (1998)Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters., , and . VLSI Design, page 12-17. IEEE Computer Society, (1998)