Author of the publication

Hardware implementation of a SHA-3 application-specific instruction set processor.

, , , , and . ICM, page 109-112. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Run-time prediction and preemption of configuration attacks on embedded process controllers., , and . SECURIT, page 135-144. ACM, (2012)Overloaded CDMA bus topology for MPSoC interconnect., and . ReConFig, page 1-7. IEEE, (2014)Design and Analysis of Convolutional Neural Layers: A Signal Processing Perspective.. IEEE Access, (2023)Interacting with Hardware Trojans over a network., , and . HOST, page 69-74. IEEE Computer Society, (2012)Enhanced Overloaded CDMA Interconnect (OCI) Bus Architecture for On-Chip Communication., and . Hot Interconnects, page 78-87. IEEE Computer Society, (2015)A Self-Contained STFT CNN for ECG Classification and Arrhythmia Detection at the Edge.. IEEE Access, (2022)Lane departure warning tracking system based on score mechanism., , , , , , and . MWSCAS, page 1-4. IEEE, (2016)Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement., , and . FPL, page 207-212. IEEE Computer Society, (2011)SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture., , , , and . ASAP, page 233-234. IEEE Computer Society, (2016)Parallel overloaded CDMA interconnect (OCI) bus architecture for on-chip communications., and . ICECS, page 621-624. IEEE, (2015)