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A Data-Sharing Aware and Scalable Cache Miss Rates Model for Multi-Core Processors with Multi-Level Cache Hierarchies., , , и . ICPADS, стр. 267-274. IEEE, (2019)An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks., , , , , , и . IEEE Trans. Vehicular Technology, 68 (5): 5100-5113 (2019)Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph., , , и . DATE, стр. 598-601. IEEE Computer Society, (2010)Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection., , , , и . CoRR, (2023)A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2197-2209 (2021)Vina-GPU 2.0: Further Accelerating AutoDock Vina and Its Derivatives with Graphics Processing Units., , , , , , , и . J. Chem. Inf. Model., 63 (7): 1982-1998 (апреля 2023)An improved point cloud denoising method in adverse weather conditions based on PP-LiteSeg network., и . PeerJ Comput. Sci., (2024)An artificial neural network model of LRU-cache misses on out-of-order embedded processors., , , и . Microprocess. Microsystems, (2017)AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations., , , и . IEEE Embed. Syst. Lett., 12 (1): 13-16 (2020)TYMER: A Yield-based Performance Model for Timing-speculation SRAM., , , , , и . DAC, стр. 1-6. IEEE, (2020)