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Disambiguation of "Meher, Pramod Kumar"

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Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic.

, , and . IEEE Trans. Computers, 62 (6): 1170-1178 (2013)

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Pramod Kumar Pandey

Pramod Kumar Magu

Pramod Kumar Bhatotia

Pramod Chandrashekhariah

Pramod Shah

 

Other publications of authors with the same name

Flexible integer DCT architectures for HEVC., and . ISCAS, page 1376-1379. IEEE, (2013)Efficient coefficient partitioning for decomposed DA-based inner-product computation., and . ISCAS, page 406-409. IEEE, (2011)Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic., , and . IEEE Trans. Computers, 62 (6): 1170-1178 (2013)Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition., and . ISCAS, page 2910-2913. IEEE, (2009)An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials., , and . ASP-DAC, page 210-215. IEEE, (2009)VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT., and . APCCAS, page 458-461. IEEE, (2006)Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT., and . IEEE Trans. Circuits Syst. Video Techn., 23 (2): 353-363 (2013)Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series., , and . iSES, page 312-315. IEEE, (2019)High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation., , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (7): 606-610 (2007)Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder., and . ASAP, page 305-309. IEEE Computer Society, (2008)