( en | de | ru )

 

Disambiguation of "Acosta, Antonio J."

Author of the publication

copydeleteadd this publication to your clipboard
New CMOS VLSI linear self-timed architectures.

, , , , , and . ASYNC, page 14-23. IEEE Computer Society, (1995)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Antonio J Levy

Antonio F J Bellote

Ursula Acosta

Lisette Acosta

Oscar Acosta

 

Other publications of authors with the same name

Modular Asynchronous Arbiter Insensitive to Metastability., , , , and . IEEE Trans. Computers, 44 (12): 1456-1461 (1995)Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions., , , , and . Int. J. Circuit Theory Appl., 44 (1): 4-20 (2016)Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures., , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 76-85. Springer, (2009)A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches., , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 209-218. Springer, (2002)Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits., , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 316-326. Springer, (2000)Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications., , and . PATMOS, page 1-8. IEEE, (2014)Effect of Temperature Variation in Experimental DPA and DEMA Attacks., and . PATMOS, page 163-168. IEEE, (2018)Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices., , , and . IEEE Trans. Emerg. Top. Comput., 9 (2): 787-796 (2021)SODS: a new CMOS differential-type structure., , , , and . IEEE J. Solid State Circuits, 30 (7): 835-838 (July 1995)A switching noise vision of the optimization techniques for low-power synthesis., , , and . ECCTD, page 156-159. IEEE, (2007)