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Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI., , , , , , , , и . IEEE J. Solid State Circuits, 49 (7): 1499-1505 (2014)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking., , , , , , , , , и 12 other автор(ы). ISSCC, стр. 452-453. IEEE, (2014)FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip., , , , , , , и . DFT, стр. 1-6. IEEE, (2021)A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance., , , , , и . ICICDT, стр. 1-4. IEEE, (2012)8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test., , , , , , , и . IRPS, стр. 12. IEEE, (2015)Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology., , , , , , , , , и 4 other автор(ы). ISQED, стр. 366-370. IEEE, (2015)Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI., , , , , и . ESSCIRC, стр. 205-208. IEEE, (2013)A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance., , , , и . ESSCIRC, стр. 313-316. IEEE, (2012)A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI., , , , , и . ESSCIRC, стр. 153-162. IEEE, (2017)