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HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks., , , , , , , , , and 1 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (8): 1543-1556 (2019)High performance training of deep neural networks using pipelined hardware acceleration and distributed memory., , , , , , , and . ISQED, page 383-388. IEEE, (2018)Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits., and . ACM Trans. Design Autom. Electr. Syst., 22 (3): 57:1-57:21 (2017)SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing., , , , , and . FPGA, page 205-214. ACM, (2016)Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC., and . 3DIC, page TS8.23.1-TS8.23.6. IEEE, (2015)Structural design optimization for deep convolutional neural networks using stochastic computing., , , , , , and . DATE, page 250-253. IEEE, (2017)Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC., and . ISCAS, page 802-805. IEEE, (2014)A multi-mode energy-efficient double-precision floating-point multiplier., and . MWSCAS, page 29-32. IEEE, (2014)Feed-forward gain compensation for CMOS continuous-time ΣΔ modulators., , and . ICECS, page 1685-1688. IEEE, (1999)A high-speed high-resolution CMOS current comparator., , and . ICECS, page 303-306. IEEE, (1999)