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Disambiguation of "Iwamoto, Hisashi"

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An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k).

, , , and . J. Multiple Valued Log. Soft Comput., 26 (1-2): 109-123 (2016)

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Hisashi Saeki

Hisashi Ochi

Hisashi Saito

Hisashi Sugiura

Hisashi Yano

 

Other publications of authors with the same name

A slice structure using the management of network traffic prediction for green IT., , , , , and . HPSR, page 250-255. IEEE, (2012)Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS., , , , , and . IEICE Trans. Commun., 96-B (7): 1819-1825 (2013)A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units., , , , and . IEICE Trans. Inf. Syst., 98-D (2): 262-271 (2015)Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure., , , , , , , and . CCNC, page 309-314. IEEE, (2016)2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving., , , , , , and . CCNC, page 97-105. IEEE, (2013)An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k)., , , and . J. Multiple Valued Log. Soft Comput., 26 (1-2): 109-123 (2016)A study on micro level traffic prediction for energy-aware routers., , , , , , and . ACM SIGOPS Oper. Syst. Rev., 47 (3): 26-33 (2013)A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application., , , , , and . IEICE Trans. Electron., 96-C (8): 1076-1082 (2013)A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)., , , and . FPGA, page 290. ACM, (2017)28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)