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Infrastructure Circuits for Lifetime Improvement of Ultra-Low Power IoT Devices.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2598-2610 (2017)

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Low energy digital circuit design using sub-threshold operation.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2005)ndltd.org (oai:dspace.mit.edu:1721.1/35527).Flexible on-chip power delivery for energy efficient heterogeneous systems., and . DAC, page 160:1-160:6. ACM, (2013)A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM., , , and . ISLPED, page 307-310. ACM, (2014)Analyzing static and dynamic write margin for nanometer SRAMs., , and . ISLPED, page 129-134. ACM, (2008)Optimizing SRAM bitcell reliability and energy for IoT applications., , and . ISQED, page 12-17. IEEE, (2016)Modeling SRAM dynamic VMIN., , , and . ICICDT, page 1-4. IEEE, (2014)A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs., , , , and . ISQED, page 341-346. IEEE, (2018)Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only)., and . FPGA, page 277. ACM, (2013)A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR., , , , , , , , , and . CICC, page 1-2. IEEE, (2023)A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy-Harvesting and Power-Management Platform with 1.2×105 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up., , and . ISSCC, page 1-3. IEEE, (2022)