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A Data Path Layout Assembler for High Performance DSP Circuits.

, , , and . DAC, page 306-311. IEEE Computer Society Press, (1990)

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REDUSA: module generation by automatic elimination of superfluous blocks in regular structures., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (9): 989-998 (1989)CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler., , , and . EURO-DAC, page 617-621. IEEE Computer Society, (1990)Cathedral-II: A Silicon Compiler for Digital Signal Processing., , , and . IEEE Des. Test, 3 (6): 13-25 (1986)A Data Path Layout Assembler for High Performance DSP Circuits., , , and . DAC, page 306-311. IEEE Computer Society Press, (1990)Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks., , , , , , and . Synthesis for Control Dominated Circuits, volume A-22 of IFIP Transactions, page 167-181. North-Holland, (1992)An intelligent module generator environment., , , and . DAC, page 730-735. IEEE Computer Society Press, (1986)DARSI: RC data reduction VLSI simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (4): 493-500 (1991)Timing optimization by bit-level arithmetic transformations., , , and . EURO-DAC, page 48-53. IEEE Computer Society, (1995)Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation., , , and . J. Electron. Test., 12 (3): 217-238 (1998)Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers., , , , , and . Synthesis for Control Dominated Circuits, volume A-22 of IFIP Transactions, page 61-71. North-Holland, (1992)