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Self-Tuning Intel Transactional Synchronization Extensions.

, and . ICAC, page 209-219. USENIX Association, (2014)

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Self-tuning Intel Restricted Transactional Memory., and . Parallel Comput., (2015)Self-Tuning Intel Transactional Synchronization Extensions., and . ICAC, page 209-219. USENIX Association, (2014)STI-BT: A Scalable Transactional Index., and . IEEE Trans. Parallel Distributed Syst., 27 (8): 2408-2421 (2016)Seer: Probabilistic Scheduling for Hardware Transactional Memory., , and . ACM Trans. Comput. Syst., 35 (3): 7:1-7:41 (2017)Time-Warp: Efficient Abort Reduction in Transactional Memory., and . ACM Trans. Parallel Comput., 2 (2): 12:1-12:44 (2015)On the use of Clocks to Enforce Consistency in the Cloud., , , , and . IEEE Data Eng. Bull., 38 (1): 18-31 (2015)ProteusTM: Abstraction Meets Performance in Transactional Memory., , , , , and . ASPLOS, page 757-771. ACM, (2016)Seer: Probabilistic Scheduling for Hardware Transactional Memory., , and . SPAA, page 224-233. ACM, (2015)Practical Parallel Nesting for Software Transactional Memory., and . DISC, volume 8205 of Lecture Notes in Computer Science, page 149-163. Springer, (2013)STI-BT: A Scalable Transactional Index., and . ICDCS, page 104-113. IEEE Computer Society, (2014)