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A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs., , , , and . ISQED, page 341-346. IEEE, (2018)Graphene Devices, Interconnect and Circuits - Challenges and Opportunities., , , and . ISCAS, page 69-72. IEEE, (2009)A Case for Thermal-Aware Floorplanning at the Microarchitectural Level., , , and . J. Instruction-Level Parallelism, (2005)Analog VLSI for robot path planning., , , and . J. VLSI Signal Process., 8 (1): 61-73 (1994)Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model., , , , and . IEEE Trans. Computers, 57 (9): 1277-1288 (2008)Using Intradisk Parallelism to Build Energy-Efficient Storage Systems., , and . IEEE Micro, 29 (1): 50-61 (2009)Temperature-Aware Computer Systems: Opportunities and Challenges., , , , , and . IEEE Micro, 23 (6): 52-61 (2003)Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2335-2344 (2016)Low-power encodings for global communication in CMOS VLSI., and . IEEE Trans. Very Large Scale Integr. Syst., 5 (4): 444-455 (1997)Low Power Design for ASIC Cores., , , and . VLSI Design, 12 (3): 317-331 (2001)