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A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.

Z. Jin, A. Hu, X. Shan, C. Zhang, J. Cui, J. Lei, and D. Liu. Microelectron. J., (February 2023)

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Ang Yang

Kianbo Ang

Jesse Ang

Ang Li

Su-Shin Ang

Other publications of authors with the same name

Analysis and optimization of seamless switching golden states of multi-modulus divider in software defined ∑-Δ Frequency synthesizer.A. Hu, D. Liu, and K. feng Zhang. Microelectron. J., (2019)An Efficient Unstructured Sparse Convolutional Neural Network Accelerator for Wearable ECG Classification Device.J. Lu, D. Liu, X. Cheng, L. Wei, A. Hu, and X. Zou. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4572-4582 (2022)A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS.C. Zhang, A. Hu, D. Liu, S. Ma, H. Li, Z. Jin, J. Liu, Y. Wang, and W. Yang. Microelectron. J., (November 2023)A 35µW Receiver Front-End with 35% wireless energy harvesting efficiency for Wearable Medical Applications.Z. Jin, A. Hu, Z. Liu, and D. Liu. ASICON, page 1-4. IEEE, (2019)Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set Extension.J. Zhang, J. Lu, D. Liu, A. Li, X. Li, S. Yang, A. Hu, and X. Zou. A-SSCC, page 1-3. IEEE, (2023)A 0.03- to 3.6-GHz Frequency Synthesizer With Self-Biased VCO and Quadrature-Input Quadrature-Output Frequency Divider.A. Hu, D. Liu, and K. Zhang. IEEE Trans. Circuits Syst. II Express Briefs, 66-II (12): 1997-2001 (2019)A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer.X. Tang, X. Zhao, A. Hu, D. Liu, and Z. Jin. Microelectron. J., (2021)A 640×512 ROIC with optimized BDI input stage and low power output buffer for CQDs-based infrared image sensor.H. Li, A. Hu, Z. Nie, D. Liu, G. Niu, L. Gao, and J. Tang. Microelectron. J., (2022)A Flexible and High-Performance Lattice-Based Post-Quantum Crypto Secure Coprocessor.A. Li, D. Liu, C. Zhang, X. Li, S. Yang, X. Liu, J. Lu, X. Zou, A. Hu, and T. Ni. IEEE Trans. Ind. Informatics, 19 (2): 1874-1883 (2023)SAS-SEINet: A SNR-Aware Adaptive Scalable SEI Neural Network Accelerator Using Algorithm-Hardware Co-Design for High-Accuracy and Power-Efficient UAV Surveillance.J. Gan, A. Hu, Z. Kang, Z. Qu, Z. Yang, R. Yang, Y. Wang, H. Shao, and J. Zhou. Sensors, 22 (17): 6532 (2022)

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Disambiguation of "Hu, Ang"

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A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.

Please choose a person to relate this publication to

Ang Yang

Kianbo Ang

Jesse Ang

Ang Li

Su-Shin Ang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hu, Ang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.

Please choose a person to relate this publication to

Ang Yang

Kianbo Ang

Jesse Ang

Ang Li

Su-Shin Ang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.