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Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product., , , , , , , , , и 6 other автор(ы). ISCA, стр. 43-56. IEEE, (2021)An Architecture of Sparse Length Sum Accelerator in AxDIMM., , , и . AICAS, стр. 1-4. IEEE, (2022)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , и 25 other автор(ы). ISSCC, стр. 330-332. IEEE, (2020)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)., , , , , , , , , и 9 other автор(ы). A-SSCC, стр. 169-172. IEEE, (2016)An FPGA-based RNN-T Inference Accelerator with PIM-HBM., , , , , , и . FPGA, стр. 146-152. ACM, (2022)A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture., , и . IEEE J. Solid State Circuits, 40 (1): 254-260 (2005)The Breakthrough Memory Solutions for Improved Performance on LLM Inference., , , , , , , , , и 13 other автор(ы). IEEE Micro, 44 (3): 40-48 (мая 2024)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond., , , , , , , , , и 10 other автор(ы). HCS, стр. 1-26. IEEE, (2021)An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control., , , , , , , и . SoC, стр. 1-4. IEEE, (2006)A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM., , , , , , и . VLSI Technology and Circuits, стр. 152-153. IEEE, (2022)