Author of the publication

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays.

, , , , and . IEICE Trans. Electron., 95-C (4): 594-599 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors., , , , , and . HiPC, volume 2913 of Lecture Notes in Computer Science, page 393-404. Springer, (2003)1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing., , , and . IEEE J. Solid State Circuits, 46 (4): 828-837 (2011)On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer., , , , , and . BioCAS, page 178-181. IEEE, (2013)Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device., , , , , , and . IEICE Trans. Electron., 95-C (4): 651-660 (2012)Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays., , , , and . IEICE Trans. Electron., 95-C (4): 594-599 (2012)0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays., , , and . IEEE J. Solid State Circuits, 45 (11): 2348-2355 (2010)Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device., , , , , , and . ISCAS, page 2299-2302. IEEE, (2012)