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Disambiguation of "Kermani, Mehran Mozaffari"

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Low-Latency Digit-Serial Systolic Double Basis Multiplier over $GF(2^m)$ Using Subquadratic Toeplitz Matrix-Vector Product Approach.

, , , , , , and . IEEE Trans. Computers, 63 (5): 1169-1181 (2014)

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Djavad Kermani

Ehssan Mozaffari

Hamid Kermani

Khalil Kermani

Khalil Kermani

 

Other publications of authors with the same name

A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard., and . FDTC, page 47-53. IEEE Computer Society, (2007)A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography., , and . IEEE Trans. Computers, 67 (11): 1594-1609 (2018)Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 2804-2812 (2015)Error Detection Constructions for ITA Finite Field Inversions Over $GF(2^m)$ on FPGA Using CRC and Hamming Codes., , and . IEEE Trans. Reliab., 72 (2): 651-661 (2023)Cryptographic Accelerators for Digital Signature Based on Ed25519., , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1297-1305 (2021)Error Detection Schemes Assessed on FPGA for Multipliers in Lattice-Based Key Encapsulation Mechanisms in Post-Quantum Cryptography., , , , and . IEEE Trans. Emerg. Top. Comput., 11 (3): 791-797 (July 2023)Time-Efficient Finite Field Microarchitecture Design for Curve448 and Ed448 on Cortex-M4., , , and . IACR Cryptol. ePrint Arch., (2023)A Comprehensive Survey on the Implementations, Attacks, and Countermeasures of the Current NIST Lightweight Cryptography Standard., , , and . CoRR, (2023)SIKE'd Up: Fast Hardware Architectures for Supersingular Isogeny Key Encapsulation., , , , and . IEEE Trans. Circuits Syst., 67-I (12): 4842-4854 (2020)High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography., , and . ARITH, page 94-101. IEEE, (2021)