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A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (8): 2030-2038 (2013)

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A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology., and . ISCAS, page 1-4. IEEE, (2017)A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit., , and . VLSIC, page 140-. IEEE, (2015)19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection., , and . ISSCC, page 326-327. IEEE, (2016)A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning., , , , and . ISSCC, page 308-310. IEEE, (2018)A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing., , , , , and . CICC, page 1-4. IEEE, (2019)SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data., , and . CICC, page 1-4. IEEE, (2014)Studying the Impact of Temperature Gradient on Electromigration Lifetime Using a Power Grid Test Structure with On-Chip Heaters., , , , and . IRPS, page 1-5. IEEE, (2023)Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited)., , , and . IRPS, page 8. IEEE, (2022)A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme., , and . VLSIC, page 130-131. IEEE, (2012)Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR)., , and . ISCAS, page 41-44. IEEE, (2015)