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A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX., , и . A-SSCC, стр. 209-212. IEEE, (2018)5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop., , , , и . ISSCC, стр. 94-95. IEEE, (2017)A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (2): 91-95 (2013)A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (3): 142-146 (2013)A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement., , , , , и . IEEE J. Solid State Circuits, 51 (8): 1902-1914 (2016)Equalized on-chip interconnect: modeling, analysis, and design.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2010)ndltd.org (oai:dspace.mit.edu:1721.1/58076).A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces., , , , и . ISSCC, стр. 1-3. IEEE, (2022)A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect., , , , и . ISSCC, стр. 308-310. IEEE, (2019)Equalized interconnects for on-chip networks: modeling and optimization framework., и . ICCAD, стр. 552-559. IEEE Computer Society, (2007)A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed Links., , , , и . ISOCC, стр. 19-20. IEEE, (2022)