( en | de | ru )

 

Disambiguation of "Wang, Chua-Chin"

Author of the publication

copydeleteadd this publication to your clipboard
On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (6): 1432-1440 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wang- Chin Kim

Chin-hsien Wang

Stephanie Chua

Siewteen Chua

Modesto Chua

 

Other publications of authors with the same name

An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method., , and . VLSI Design, 14 (2): 193-202 (2002)Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library., , and . VLSI Design, 11 (4): 331-338 (2000)A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits., , , and . Circuits Syst. Signal Process., 37 (4): 1692-1703 (2018)A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit., , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (12): 3478-3482 (2021)A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 4860-4871 (2022)200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process., and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (9): 3163-3166 (2021)Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems., , , and . ASICON, page 1-4. IEEE, (2019)A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation., , and . ICECS, page 1018-1021. IEEE, (2008)Mixed-voltage I/O buffer using 0.35 μm CMOS technology., , and . ICECS, page 850-853. IEEE, (2008)A 32-bit carry lookahead adder design using complementary all-N-transistor logic., , and . ICECS, page 706-709. IEEE, (2008)