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System-level design for test of fully differential analog circuits.

, , and . IEEE J. Solid State Circuits, 31 (10): 1526-1534 (1996)

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Functional Test Generation for FSMs by Fault Extraction., and . DAC, page 712-715. ACM Press, (1994)Reducing test application time in scan design schemes., and . VTS, page 367-373. IEEE Computer Society, (1995)SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP)., , , , , and . ISQED, page 1-6. IEEE, (2022)System-level design for test of fully differential analog circuits., , and . IEEE J. Solid State Circuits, 31 (10): 1526-1534 (1996)Data parallel fault simulation., and . IEEE Trans. Very Large Scale Integr. Syst., 7 (2): 183-190 (1999)Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis., and . FTCS, page 504-511. IEEE Computer Society, (1991)A dependence graph-based approach to the design of algorithm-based fault tolerant systems., and . FTCS, page 122-129. IEEE Computer Society, (1990)A C-Testable Carry-Free Divider., , and . ICCD, page 206-213. IEEE Computer Society, (1993)An analysis of the delay defect detection capability of the ECR test method., , and . ITC, page 1060-1069. IEEE Computer Society, (2000)Optimal test-set generation for parametric fault detection in switched capacitor filters., , and . Asian Test Symposium, page 72-77. IEEE Computer Society, (2000)