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Disambiguation of "Iwagaki, Tsuyoshi"

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Efficient path delay test generation based on stuck-at test generation using checker circuitry.

, , , and . ICCAD, page 418-423. IEEE Computer Society, (2007)

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Tsuyoshi Takagi

Tsuyoshi Matsuda

 

Other publications of authors with the same name

An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis., , , and . ITC-Asia, page 55-60. IEEE, (2019)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)Novel Register Sharing in Datapath for Structural Robustness against Delay Variation., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (4): 1044-1053 (2008)Logic simplification by minterm complement for error tolerant application., , , and . ICCD, page 94-100. IEEE Computer Society, (2015)A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties., and . DELTA, page 293-296. IEEE Computer Society, (2010)Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (12): 1464-1471 (2020)Compact and Accurate Digital Filters Based on Stochastic Computing., , , , and . IEEE Trans. Emerg. Top. Comput., 7 (1): 31-43 (2019)Compact and accurate stochastic circuits with shared random number sources., , , , and . ICCD, page 361-366. IEEE Computer Society, (2014)Safe clocking register assignment in datapath synthesis., , and . ICCD, page 120-127. IEEE Computer Society, (2008)Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation., , and . ETS, page 48-53. IEEE Computer Society, (2005)