Author of the publication

Dynamic voltage scaling for SEU-tolerance in low-power memories.

, and . VLSI-SoC, page 207-212. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Non-uniform clock mesh optimization with linear programming buffer insertion., , and . DAC, page 74-79. ACM, (2010)Process-induced skew reduction in nominal zero-skew clock trees., , and . ASP-DAC, page 84-89. IEEE, (2006)CMCS: Current-Mode Clock Synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1054-1062 (2017)Current-mode clock distribution., and . ISCAS, page 1203-1206. IEEE, (2014)Dynamic voltage scaling for SEU-tolerance in low-power memories., and . VLSI-SoC, page 207-212. IEEE, (2012)High-Performance, Low-Power Resonant Clocking: Embedded tutorial., and . ICCAD, page 742-745. ACM, (2012)DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 2108-2117 (2018)HCDN: Hybrid-Mode Clock Distribution Networks., and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 251-262 (2019)Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor., , , , , , and . IEEE Trans. Computers, 54 (8): 998-1012 (2005)VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS., , and . ISQED, page 506-515. IEEE, (2012)