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Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures., , , , and . IEEE Trans. Computers, 52 (1): 4-20 (2003)A New Framework for Elimination-Based Data Flow Analysis Using DJ Graphs., , and . ACM Trans. Program. Lang. Syst., 20 (2): 388-435 (1998)Minimizing communication in rate-optimal software pipelining for stream programs., , , and . CGO, page 210-217. ACM, (2010)Mapping the LU decomposition on a many-core architecture: challenges and solutions., and . Conf. Computing Frontiers, page 71-80. ACM, (2009)Topic 08+13: Instruction-Level Parallelism and Computer Architecture., , , , , , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 385. Springer, (2001)An Implementation of the Codelet Model., , and . Euro-Par, volume 8097 of Lecture Notes in Computer Science, page 633-644. Springer, (2013)If-Conversion in SSA Form., and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 336-345. Springer, (2004)Multithreaded algorithms for the fast Fourier transform., , , and . SPAA, page 176-185. ACM, (2000)Towards an Efficient Hybrid Dataflow Architecture Model., , and . PARLE (1), volume 505 of Lecture Notes in Computer Science, page 355-371. Springer, (1991)Polytasks: A Compressed Task Representation for HPC Runtimes., , , , and . LCPC, volume 7146 of Lecture Notes in Computer Science, page 268-282. Springer, (2011)