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Другие публикации лиц с тем же именем

Energy efficient design of CNFET-based multi-digit ternary adders., , и . Microelectron. J., (2018)Design of CNTFET-based Ternary Logic circuits using Low power Encoder., , и . iSES, стр. 142-147. IEEE, (2022)Design Methodologies for Ternary Logic Circuits., и . ISMVL, стр. 192-197. IEEE Computer Society, (2018)A New Design of an N-Bit Reversible Arithmetic Logic Unit., , , , и . ISED, стр. 224-225. IEEE Computer Society, (2014)CNFET based ternary magnitude comparator., , , и . ISCIT, стр. 942-946. IEEE, (2012)Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders., , , , , и . ISVLSI, стр. 225-230. IEEE Computer Society, (2012)Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation., и . J. Circuits Syst. Comput., (января 2024)FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design., , и . ISCAS, стр. 1-5. IEEE, (2020)A Novel Low Power Ternary Multiplier Design using CNFETs., , и . VLSID, стр. 25-30. IEEE, (2020)Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs., , , и . iSES, стр. 280-283. IEEE, (2019)