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Disambiguation of "Ahmed, Syed Ershad"

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Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.

, , , , , and . ISVLSI, page 225-230. IEEE Computer Society, (2012)

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Ahmed Mian Syed

Syed Rafique Ahmed

Syed Rafeeq Ahmed

Syed Naeem Ahmed

Djafar Ershad

 

Other publications of authors with the same name

A Hybrid Energy Efficient Digital Comparator., , and . VLSID, page 567-568. IEEE Computer Society, (2016)Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders., , , , , and . ISVLSI, page 225-230. IEEE Computer Society, (2012)A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block., , , , , and . ISED, page 100-105. IEEE Computer Society, (2011)Compressor based hybrid approximate multiplier architectures with efficient error correction logic., , and . Comput. Electr. Eng., 104 (Part): 108407 (2022)An Improved Logarithmic Multiplier for Media Processing., and . J. Signal Process. Syst., 91 (6): 561-574 (2019)Design of Energy Efficient Posit Multiplier., , , and . ACM Great Lakes Symposium on VLSI, page 645-651. ACM, (2023)Power Efficient Approximate Ternary Subtractor for Image Processing Applications., , , , , and . iSES, page 127-130. IEEE, (2023)Design of Prefix-Based Optimal Reversible Comparator., , , , , and . ISVLSI, page 201-206. IEEE Computer Society, (2012)A Unified Architecture for BCD and Binary Adder/Subtractor., , , , , and . DSD, page 426-429. IEEE Computer Society, (2011)Increment/decrement/2's complement/priority encoder circuit for varying operand lengths., , , , , and . ISCIT, page 472-477. IEEE, (2011)