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Layered, Multi-Threaded, High-Level Performance Design.

, , and . DATE, page 10954-10959. IEEE Computer Society, (2003)

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Slack allocation for yield improvement in NoC-based MPSoCs., , and . ISQED, page 738-746. IEEE, (2010)Architectural Partitioning for System Level Design., and . DAC, page 62-67. ACM Press, (1989)Synthesis of Pipelined Instruction Set Processors., and . DAC, page 583-588. ACM Press, (1993)Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 805-812 (2001)Synthesis of application-specific memory designs., and . IEEE Trans. Very Large Scale Integr. Syst., 5 (1): 101-111 (1997)Event-based re-training of statistical contention models for heterogeneous multiprocessors., , and . CODES+ISSS, page 69-74. ACM, (2007)Linking the Behavioral and Structural Domains of Representation for Digital System Design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 6 (1): 103-110 (1987)Address generation for memories containing multiple arrays., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (5): 377-385 (1998)Architectural partitioning for system level synthesis of integrated circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (7): 847-860 (1991)The VLSI Design Automation Assistant: An IBM System/370 Design., and . IEEE Des. Test, 1 (1): 60-69 (1984)