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SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative.

, , , , , , , and . Microprocess. Microsystems, (November 2021)

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VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (2): 177-186 (2022)Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative., , , , , and . ApplePies, volume 1110 of Lecture Notes in Electrical Engineering, page 378-385. Springer, (2023)CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes., , , , , , and . ApplePies, volume 866 of Lecture Notes in Electrical Engineering, page 31-38. Springer, (2021)An implementation of the 802.1AE MAC Security Standard for in-car networks., , , , , and . WF-IoT, page 24-28. IEEE Computer Society, (2015)Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm., , , , , , and . Sensors, 20 (7): 1869 (2020)A PUF-Based Secure Boot for RISC-V Architectures., , , , , , and . ApplePies, volume 1110 of Lecture Notes in Electrical Engineering, page 87-94. Springer, (2023)A Simulated Approach to Evaluate Side Channel Attack Countermeasures for the Advanced Encryption Standard., , , , and . PRIME, page 77-80. IEEE, (2018)Analysis of Cybersecurity Weakness in Automotive In-Vehicle Networking and Hardware Accelerators for Real-Time Cryptography., , , , and . ApplePies, page 11-18. Springer, (2018)Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms., , , , , and . ICECS, page 775-778. IEEE, (2019)On the Usage of Isomorphic Fields in Hardware AES Modules for Optimizing the Efficiency., and . ApplePies, volume 1110 of Lecture Notes in Electrical Engineering, page 55-61. Springer, (2023)