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New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm.

, and . ISQED, page 425-430. IEEE, (2011)

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Sub-threshold Circuit Design with Shrinking CMOS Devices., , , and . ISCAS, page 2541-2544. IEEE, (2009)New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm., and . ISQED, page 425-430. IEEE, (2011)Improving SRAM Vmin and yield by using variation-aware BTI stress., , , , , and . CICC, page 1-4. IEEE, (2010)Nonrandom Device Mismatch Considerations in Nanoscale SRAM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1211-1220 (2012)Limits of bias based assist methods in nano-scale 6T SRAM., , , and . ISQED, page 1-8. IEEE, (2010)HTOL SRAM Vmin shift considerations in scaled HKMG technologies., , , , , , , , , and 2 other author(s). CICC, page 1-4. IEEE, (2014)Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing., , , , , , , , , and 3 other author(s). IRPS, page 6. IEEE, (2015)Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications., , and . IOLTS, page 209-210. IEEE, (2017)Enchanced multi-threshold (MTCMOS) circuits using variable well bias., , , , , and . ISLPED, page 165-169. ACM, (2001)Tracking On-Chip Age Using Distributed, Embedded Sensors., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (11): 1974-1985 (2012)