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High-performance code generation for stencil computations on GPU architectures., , and . ICS, page 311-320. ACM, (2012)Equivalence of Dataflow Graphs via Rewrite Rules Using a Graph-to-Sequence Neural Model., , and . CoRR, (2020)Polyhedral-based data reuse optimization for configurable computing., , , and . FPGA, page 29-38. ACM, (2013)Inside Vaucanson., , , , and . CIAA, volume 3845 of Lecture Notes in Computer Science, page 116-128. Springer, (2005)Distributed memory code generation for mixed Irregular/Regular computations., , , , , , and . PPoPP, page 65-75. ACM, (2015)Effective resource management for enhancing performance of 2D and 3D stencils on GPUs., , , , , and . GPGPU@PPoPP, page 92-102. ACM, (2016)PALMED: Throughput Characterization for Superscalar Architectures., , , , , , and . CGO, page 106-117. IEEE, (2022)On Using the Roofline Model with Lower Bounds on Data Movement., , , , , , and . ACM Trans. Archit. Code Optim., 11 (4): 67:1-67:23 (2014)A stencil compiler for short-vector SIMD architectures., , , , , and . ICS, page 13-24. ACM, (2013)POSTER: Hybrid Data Dependence Analysis for Loop Transformations., , , and . PACT, page 439-440. ACM, (2016)