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Improving the Security of Dual-Rail Circuits.

, , , and . CHES, volume 3156 of Lecture Notes in Computer Science, page 282-297. Springer, (2004)

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Synthesis of SI Circuits from Burst-Mode Specifications., , , , and . DATE, page 366-369. IEEE, (2021)Improving the Security of Dual-Rail Circuits., , , and . CHES, volume 3156 of Lecture Notes in Computer Science, page 282-297. Springer, (2004)A CMOS-based neural implantable optrode for optogenetic stimulation and electrical recording., , , , , , and . BioCAS, page 1-4. IEEE, (2015)Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis., , and . ACSD, page 104-113. IEEE Computer Society, (2016)GALS synthesis and verification for xMAS models., , and . DATE, page 1419-1424. ACM, (2015)Synthesis from Waveform Transition Graphs., , and . ASYNC, page 60-67. IEEE, (2019)Significance-Driven Logic Compression for Energy-Efficient Multiplier Design., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)Towards power-elastic systems through concurrency management., , , , , , , and . IET Comput. Digit. Tech., 6 (1): 33-42 (2012)Design and Implementation of Reconfigurable Asynchronous Pipelines., , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1527-1539 (2020)An Excitation Time Model for General-purpose Memristance Tuning Circuit., , , and . ISCAS, page 1-5. IEEE, (2018)