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Disambiguation of "Veeramachaneni, Sreehari"

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Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.

, , , , and . VLSI Design, page 324-329. IEEE Computer Society, (2007)

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Other publications of authors with the same name

Design and Analysis of Obfuscated Full Adders., , , and . ICM, page 49-52. IEEE, (2021)Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications., , , , and . iSES, page 210-215. IEEE, (2021)A High Performance Unified BCD and Binary Adder/Subtractor., , , and . ISVLSI, page 211-216. IEEE Computer Society, (2009)Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format., , , , and . ISVLSI, page 343-350. IEEE Computer Society, (2007)A low power, variable resolution two-step flash ADC., , , , and . ACM Great Lakes Symposium on VLSI, page 39-44. ACM, (2010)Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems., , and . VLSID, page 678-683. IEEE, (2024)Energy efficient signed and unsigned radix 16 booth multiplier design., , , and . Comput. Electr. Eng., (2021)A low-error, memory-based fast binary antilogarithmic converter., , , , and . Int. J. Circuit Theory Appl., 49 (7): 2214-2226 (2021)Novel architectures for efficient (m, n) parallel counters., , , and . ACM Great Lakes Symposium on VLSI, page 188-191. ACM, (2007)A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor., , , , , and . VLSI Design, page 547-552. IEEE Computer Society, (2008)